|ARM launches PR attack on RISC-V|
|By Thom Holwerda on 2018-07-09 19:18:46|
Anybody remember Microsoft's "get the facts" campaign? Well, ARM is having its "get the facts" moment, with the British company launching a site to disparage the open source RISC-V architecture.
The instruction set architecture (ISA) is the foundation of all chip or System-on-Chip (SoC) products. It is therefore one of the most fundamental design choices you will make. If you are considering using an open-source ISA, such as RISC-V, it is critical to understand the key factors you should consider as part of your go-to-market strategy.
It seems odd for ARM - riding high as it is - to attack RISC-V like this, which seems to barely be making a dent anywhere.
|RE: Comment by FlyingJester|
|By kwan_e on 2018-07-11 00:48:33|
> Someone felt threatened at ARM. This is a knee jerk kind of action which is quite common in general. |
The fallout is going to cost the PR deparment an arm and a leg.
|- Score: 3|
|RE: Comment by Kroc|
|By Danmelbourne on 2018-07-11 10:51:07|
|I don't know how that quote ever got legs. Nobody who works in PR or comms believes that, that's for sure!! Companies measure the damage to their brand value from bad publicity in the hundreds of millions of dollars.|
|- Score: 2|
|By garyd on 2018-07-11 17:37:21|
Even folks at ARM thought this was a low blow according to this latest from El Reg: https://www.theregister.co.uk/201... |
Edited 2018-07-11 17:37 UTC
|- Score: 1|
|No, never RISC|
|By Nit-0.0 on 2018-07-11 18:01:19|
Never Risc, too masochistic only makes people use more high-level languages. |
Rather Eisc, Extended Instruction Set, making ASM less masochistic, and reducing the want for using high-level languages.
From nyt.cloud : https://nyt.cloud/showthread.php?...
"An OS is I/O via virtualized nodes, signal routing (scheduling etc) and usually a visual user interface. Programmed with a code-sequence of a certain dialect, usually Esthetic C. Peak jitter below 200μs converges to optimal. Streaming conventions could be implemented in a new standard, and protocol aswell, Could even be a whole new language with bytecode directly transported to CPU, combining scripting, interpreted, and native speed, by adding more instructions, getting several "clocks" in 1. Particulary since a lot of C is just assembly macros anyway, giving a less masochistic machine code. A lot of DSP are clear candidates, a 4pole filter (one input, one output), can be combined into a one clock operation aswell. JSR could take arguments. And ofcourse commonly used functions. Even larger things that has just one input, and one output. And this could even be done in parallel. Where instead of HTML commands, this for swiftness and low-latency. Why not even have parallel OS functions on multiple cpus, for common things like audio, and other low-latency I/O, getting better response overall. Buses could be parallelized on the mainboard aswell. And with all digital distribution goods marked with author, county/country, and automatically delegated a fair non-selfrejecting welldefined value - Delyar. Code components for OS, also being digitalgoods etc, decentralized independent author news, scholarship, media etc. Giving optimal network synergistics."
Do YOU not want to rid yourself of "centrality makes things work?" De-centralized online work, for any place.
More at nyt.cloud BBS.
Edited 2018-07-11 18:02 UTC
|- Score: -1|
|RE: First they ignore you, then they laugh at you, then ...|
|By Megol on 2018-07-13 09:38:49|
> ... they fight you, then you win. |
So they already ignored and laughed at RISC-V. I guess RISC-V will win soon.
Just that nobody laughed at them, nobody have fought them. And there are plenty of crap that didn't win even though everybody laughed and fought them - like Germanische Neue Medizine.
I am hopefull.
That yet another standard ISA can replace many other standard ISAs? Perhaps nice. But I'm not sure RISC V is the one I'd like to see as the replacement.
|- Score: 2|
|RE: Lots of early work|
|By Megol on 2018-07-13 09:47:00|
> I think that from a business perspective, license cost is probably not a huge win for RISC-V. Designs like SuperH and UltraSparc already exist as open source hardware designs without license costs, and already have full support in Linux and BSDs (along with Illumos and several others for UltraSparc), and mature compiler toolchain support. |
With ARM one contacts them and get a license to a tested core often tested and optimized for the particular process one want to use. With RISC V one can download a non-optimized core using a non-standard development system and have to port it to the process of choice oneself. And then there's the support from experienced people from ARM.
That can change in the future but it's the current state of things. But even in the future there may be x companies providing support and testing of RISC V cores each of which have to pay the costs for that.
RISC V also supports customization which is a potential problem especially as the support companies probably want to make their offering stand out from the rest - a danger of fragmentation.
|- Score: 2|
|RE: Comment by kurkosdr|
|By zima on 2018-07-13 18:25:03|
|PS. Also, being proprietary didn't stop Windows Mobile/Phone from becoming sort of quite fragmented, across versions...|
|- Score: 2|